1. Field of the Invention
This invention relates generally to memory controllers in computer systems. More particularly this invention relates to controlling an order in which memory fetches are made.
2. Description of the Related Art
Modern computer systems comprise one or more processors that need rapid access to data stored in a memory in order to achieve high throughput from the one or more processors. The computer systems typically have a memory controller between the processors and the memory. Requests are sent on a processor bus and are queued up in a read queue in the memory controller. The memory controller schedules read accesses to the memory, queues up data read from the memory, and transmits the data for transmission to the processors.
If the read queue becomes full, no further requests can be accepted by the memory controller. This situation degrades throughput and is therefore undesirable.
Therefore, there is a need for a method and apparatus for reducing or eliminating occurrences when the read queue becomes full.